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experiment_picosdr [2016/03/22 14:27] – [Setup with GRC] lbesemeexperiment_picosdr [2016/03/22 16:34] – [Setup with GRC] lbeseme
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 This block is used to configure the RX path for one card of one board (a 2x2 Pico has one board with 2 cards). This block is used to configure the RX path for one card of one board (a 2x2 Pico has one board with 2 cards).
  
 +Let's explain all parameters you have to set: 
 +  * **Target ID** -> This correspond to the ID of the corresponding Carrier Perseus Board block. 
 +  * **Block priority** -> used to init one card before an other. 
 +  * **Card number** -> Used to specify either you are using card 1 or 2. 
 +  * **Enable** -> Allow to disable a path. 
 +  * **Reference** -> Must be internal for card 1 and external for card 2. 
 +  * **RX frequency** -> Baseband frequency. 
 +  * **Data rate** -> Must twice the sample rate (because of the I/Q signal). 
 +  * **Band** -> Must be set regarding your baseband frequency. 
 +  * **Update Rate** -> How often to update the gain. This value is in Hertz. 
 +  * **RX LNA gain** -> Receive Low Noise Amplifier gain. 
 +  * **RX VGA1 gain** -> Receive amplifier 1. 
 +  * **RX gain 2** -> Receive amplifier 2. Can be set from 0 to 30 dB. 
 +  * **RX gain 3** -> Receive amplifier 3. Can be set from -13 dB to 18 dB. 
 +  * **RX Low Pass Filter Bandwith** -> This is a configurable analog filter within the RX path. You may set it to any value in the available list. The values are bandwidths on each side of the center frequencies. 
 +  * **RX Band-Pass Filter** -> This is to select a band-pass filter from the filter bank. 
 +  * **Reference Clock Control** -> This is to select who controls the Reference Clock between the Host and the FPGA. Select Host. 
 +  * **Radio Frequency Control** -> This is to select who controls the Radio Frequency between the Host and the FPGA. Select Host. 
 +  * **RX Gain Control** -> This is to select who controls the RX Gain between the Host and the FPGA. Select Host. 
 +  * **PLL/CPLD Control** -> This is to select who controls the PLL/CPLD(io expanders) between the Host and the FPGA. Select Host.
  
 ## Setup with python project ## Setup with python project
  
  
experiment_picosdr.txt · Last modified: 2016/03/22 18:15 by lbeseme

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