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experiment_picosdr [2016/03/22 16:38]
lbeseme [Setup with GRC]
experiment_picosdr [2016/03/22 18:15]
lbeseme [Setup with GRC]
Line 73: Line 73:
   * **RX Gain Control** -> This is to select who controls the RX Gain between the Host and the FPGA. Select Host.   * **RX Gain Control** -> This is to select who controls the RX Gain between the Host and the FPGA. Select Host.
   * **PLL/CPLD Control** -> This is to select who controls the PLL/CPLD(io expanders) between the Host and the FPGA. Select Host.   * **PLL/CPLD Control** -> This is to select who controls the PLL/CPLD(io expanders) between the Host and the FPGA. Select Host.
 +
 +#### Radio420 TX
 +
 +This block is used to configure the TX path for one card of one board (a 2x2 Pico has one board with 2 cards).
 +
 +Let's explain all parameters you have to set:
 +  * **Target ID** -> This correspond to the ID of the corresponding Carrier Perseus Board block.
 +  * **Block priority** -> used to init one card before an other.
 +  * **Card number** -> Used to specify either you are using card 1 or 2.
 +  * **Enable** -> Allow to disable a path.
 +  * **Reference** -> Must be internal for card 1 and external for card 2.
 +  * **TX frequency** -> Baseband frequency.
 +  * **Data rate** -> Must twice the sample rate (because of the I/Q signal).
 +  * **Automatic Calibration** -> When automatic calibration is enabled, a calibration algorithm will be run during initialization to minimize LO leakage, IQ gain and phase imbalance. It is recommended to enable it.
 +  * **Band** -> Must be set regarding your baseband frequency.
 +  * **Update Rate** -> How often to update the gain. This value is in Hertz.
 +  * **TX VGA1 gain** -> Transmit amplifier 1. Can be set from -35 dB to -4 dB.
 +  * **TX VGA2 gain** -> Transmit amplifier 2. Can be set from 0 to 25 dB.
 +  * **TX gain 3** -> Transmist amplifier 3. Can be set from -13 dB to 18 dB.
 +  * **TX Low Pass Filter Bandwidth** -> This is a configurable analog filter within the TX path. You may set it to any value in the available list. The values are bandwidths on each side of the center frequencies.
 +  * **Reference Clock Control** -> This is to select who controls the Reference Clock between the Host and the FPGA. Select Host.
 +  * **Radio Frequency Control** -> This is to select who controls the Radio Frequency between the Host and the FPGA. Select Host.
 +  * **RX Gain Control** -> This is to select who controls the RX Gain between the Host and the FPGA. Select Host.
 +  * **PLL/CPLD Control** -> This is to select who controls the PLL/CPLD(io expanders) between the Host and the FPGA. Select Host.
 +
 +
 +#### Custom registers
 +
 +As it is explained before, we have to set 3 custom registers in order to make the bitstream work properly.
 +
 +The block Custom Register has 5 parameters to set :
 +  * **Target Id** -> This correspond to the ID of the corresponding Carrier Perseus Board block.
 +  * **Block priority** -> Used to init custom registers after RX/TX paths.
 +  * **Register Index** -> The index of the custom register, from 0 to 31.
 +  * **Register Value** -> The value that is written initially. This can also be updated in real-time using a variable.
 +  * **Update Rate** -> How often to update the register. This value is in Hertz.
 +
 +
 +In our case, register 4 must be set to 0 (async mode), register 3 to 0 with a constant source block feeding a 1 in the input port, and register 1 to 6.
  
 ## Setup with python project ## Setup with python project
  
  
experiment_picosdr.txt ยท Last modified: 2016/03/22 18:15 by lbeseme