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experiment_picosdr [2016/03/22 16:56]
lbeseme [Setup with GRC]
experiment_picosdr [2016/03/22 18:15] (current)
lbeseme [Setup with GRC]
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   * **RX Gain Control** -> This is to select who controls the RX Gain between the Host and the FPGA. Select Host.   * **RX Gain Control** -> This is to select who controls the RX Gain between the Host and the FPGA. Select Host.
   * **PLL/CPLD Control** -> This is to select who controls the PLL/CPLD(io expanders) between the Host and the FPGA. Select Host.   * **PLL/CPLD Control** -> This is to select who controls the PLL/CPLD(io expanders) between the Host and the FPGA. Select Host.
 +
 +
 +#### Custom registers
 +
 +As it is explained before, we have to set 3 custom registers in order to make the bitstream work properly.
 +
 +The block Custom Register has 5 parameters to set :
 +  * **Target Id** -> This correspond to the ID of the corresponding Carrier Perseus Board block.
 +  * **Block priority** -> Used to init custom registers after RX/TX paths.
 +  * **Register Index** -> The index of the custom register, from 0 to 31.
 +  * **Register Value** -> The value that is written initially. This can also be updated in real-time using a variable.
 +  * **Update Rate** -> How often to update the register. This value is in Hertz.
 +
 +
 +In our case, register 4 must be set to 0 (async mode), register 3 to 0 with a constant source block feeding a 1 in the input port, and register 1 to 6.
  
 ## Setup with python project ## Setup with python project
  
  
experiment_picosdr.txt ยท Last modified: 2016/03/22 18:15 by lbeseme