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fpga_phy_zigbee [2017/12/12 14:33]
ooubejja [Transmitter]
fpga_phy_zigbee [2017/12/14 16:25] (current)
ooubejja [What's new here ?]
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 As seen in the previous tutorials, operations such as FFT, MUX/DEMUX, encoding, modulation,​... are processed via GNU Radio blocks all over the flow graph. In other words, the transmitted waveform is "soft shaped"​ by GNU Radio. ​ As seen in the previous tutorials, operations such as FFT, MUX/DEMUX, encoding, modulation,​... are processed via GNU Radio blocks all over the flow graph. In other words, the transmitted waveform is "soft shaped"​ by GNU Radio. ​
 The goal of this tutorial is to transmit IEEE 802.15.4 packets with a "​Hard"​ transmitter,​ it means that the waveform is generated by the PicoSDR, by taking a ''​.hex''​ file as an input and processing it through an FPGA design, using [[http://​whatis.techtarget.com/​definition/​IP-core-intellectual-property-core|IP cores]] written in hardware description language (HDL) code.  ​ The goal of this tutorial is to transmit IEEE 802.15.4 packets with a "​Hard"​ transmitter,​ it means that the waveform is generated by the PicoSDR, by taking a ''​.hex''​ file as an input and processing it through an FPGA design, using [[http://​whatis.techtarget.com/​definition/​IP-core-intellectual-property-core|IP cores]] written in hardware description language (HDL) code.  ​
-In this tutorial, we will see how to transmit and receive IEEE 802.15.4 packets using a .hex file as an input and a [[custom Bitstream]] of a IEEE 802.15.4 PHY Layer Transmitter targeting the Xilinx FPGA [[https://​www.google.fr/​url?​sa=t&​rct=j&​q=&​esrc=s&​source=web&​cd=2&​ved=0ahUKEwi_197x2-bXAhUHrRQKHXmRCWQQFggxMAE&​url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fdata_sheets%2Fds150.pdf&​usg=AOvVaw0Z12Npy0fD0V2OybYMhTkH|Virtex6]] of the [[https://​www.nutaq.com/​products/​picosdr|PicoSDR]] ​  +In this tutorial, we will see how to transmit and receive IEEE 802.15.4 packets using a .hex file as an input and a custom Bitstream of a IEEE 802.15.4 PHY Layer Transmitter targeting the Xilinx FPGA [[https://​www.google.fr/​url?​sa=t&​rct=j&​q=&​esrc=s&​source=web&​cd=2&​ved=0ahUKEwi_197x2-bXAhUHrRQKHXmRCWQQFggxMAE&​url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fdata_sheets%2Fds150.pdf&​usg=AOvVaw0Z12Npy0fD0V2OybYMhTkH|Virtex6]] of the [[https://​www.nutaq.com/​products/​picosdr|PicoSDR]] ​  
  
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 We will need some blocks of the module [[https://​github.com/​CorteXlab/​gr-cortexlab|gr-cortexlab]]. Normally, if you followed the previous tutorials (highly suggested!),​ you might have started by installing [[building_a_toolchain|The FIT/​CorteXlab Toolchain]],​ which automatically installs this module. We will need some blocks of the module [[https://​github.com/​CorteXlab/​gr-cortexlab|gr-cortexlab]]. Normally, if you followed the previous tutorials (highly suggested!),​ you might have started by installing [[building_a_toolchain|The FIT/​CorteXlab Toolchain]],​ which automatically installs this module.
  
-==== Download bitstream ​==== +==== Find the Bitstream ​==== 
-In order to use the FPGA Transmitter design, we will have to load the custom ​bitstream ​on the transmitter node(s). The Bitstream can be found [[here]] +In order to use the FPGA Transmitter design, we will have to load the custom ​Bitstream ​on the transmitter node(s). The Bitstream ​is loaded in the Airlock server of CorteXlab, and can be found in :  
-The receiver node(s) will run the default ​bitstream ​(Pass-through design)+ 
 +''/​cortexlab/​fpga/​pico_tx802154_sx315.bit''​ 
 + 
 +Copy the file in your main directory : 
 +<​code>​ 
 +you@srvairlock:​~$ cp /​cortexlab/​bitstreams/​pico_tx802154_sx315.bit . 
 +</​code>​ 
 + 
 +//The receiver node(s) will run the default ​Bitstream ​(Pass-through design)//
  
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   * ATTENTION : **Channel** parameter has to be set to **__3__** as in the previous image. That's the only channel that allows access to the custom design.   * ATTENTION : **Channel** parameter has to be set to **__3__** as in the previous image. That's the only channel that allows access to the custom design.
 +
 + * **Custom Register** (CR 1 & 4)
 +
 +  * Set CR1 value to 0 to enable the transmitter
 +  * Set CR4 value to 0 to disable MIMO synchronization
  
  * **Radio420 **   * **Radio420 ** 
-  * It is mandatory to initialize ​ALL radio modules within the PicoSDRThe PicoSDR 2x2 contains ​RF Transceiver, it means we will have 2 ''​Radio420 TX''​ blocks and 2 ''​Radio420 RX''​ blocks  ​+  * The Radio420x is a Multimode SDR [[https://​en.wikipedia.org/​wiki/​FPGA_Mezzanine_Card|FMC]] RF transceiver. PicoSDR 2x2 contains 2 Radio420M modules which are MIMO capable //(M for MIMO, pretty smart, huh ?)//. It is mandatory to initialize ​BOTH radio cards, even if only 1 is usedSo, since our device ​contains ​2 Radio420M transceivers, it means we will have 2 ''​Radio420 TX''​ blocks and 2 ''​Radio420 RX''​ blocks. Here is a [[https://​www.nutaq.com/​sites/​default/​files/​Radio420x_V1.3_03_24_2014_web.pdf|product sheet]] for more info.  
 +  * To be short, add 2 ''​Radio420 TX''​ blocks and 2 ''​Radio420 RX''​ blocks 
 +  * Now, we only need one transmitter per node, so make sure to enable only the Radio420 TX of Card 1, and set the gain values as following :  
  
 {{ :​radio420.png?​250 |}} {{ :​radio420.png?​250 |}}
  
- **Custom Register** (CR 1 & 4)+  ​For the 3 remaining ''​Radio420''​ blocks, we only need to disable them by setting the __Enable__ parameter to __False__
  
-  * Set CR1 value to 0 to enable the transmitter 
-  * Set CR4 value to 0 to disable MIMO synchronization 
  
 //If you don't get this part, have a look [[from_gnuradio_to_cortxlab_pico|here]].//​ //If you don't get this part, have a look [[from_gnuradio_to_cortxlab_pico|here]].//​
  
-There isn't that much done in here since all baseband processing is done by the FPGA. All that is left is to connect a ''​**File Source**''​ block to the ''​**RTDEx Sink**''​ block, and specify the absolute path to your "​.hex"​ file in ''​**File Source**''​ block parameters :+There isn't that much left in here since all baseband processing is done by the FPGA. All you have to do now is to connect a ''​**File Source**''​ block to the ''​**RTDEx Sink**''​ block, and specify the absolute path to your "​.hex"​ file in ''​**File Source**''​ block parameters :
 {{ :​filesource.png?​400 |}} {{ :​filesource.png?​400 |}}
  
-The final flow-graph should look like this : +The final flow-graph ​of your transmitter ​should look like this : 
  
 {{ :​ieee802154_tx_pico.grc.png?​400 |}} {{ :​ieee802154_tx_pico.grc.png?​400 |}}
fpga_phy_zigbee.1513085596.txt.gz · Last modified: 2017/12/12 14:33 by ooubejja