Here you will find documentation and how-to about the environment used by CorteXlab and provided to users.
The process of running experiments on the FIT/CorteXlab testbed involves several steps:
There 26 USRPs installed in the FIT/CorteXlab room.
TX/RX
and RX2
ports of all USRPs. In the case the TX/RX
ports are used, then only half-duplex is supportedexternal clock source
in the USRP sink or source configuration.external clock source
in the USRP sink or source configuration.Find here tutorials on how to use them
A hierarchy of octoclocks allow the reference and timing distribution to all USRPs in CorteXlab. All cables are of same length (5m between master and slave octoclocks and 10m between slave octoclocks and USRPs). The connection layout is as shown below. The octoclock 0 is the master and the octoclocks 1-4 are the slave ones.
The octoclock produces a PPS signal that has a period of 1s and remains high during 200ms and low 800ms as shown below:
The PPS signals between the slave octoclocks in the room are mismatched by a maximum of 800ps as shown below (examples):
Between nodes 28 (connected to octoclock 3) and 31 (connected to octoclock 4)
Between nodes 31 (connected to octoclock 4) and 14 (connected to octoclock 2)
Between nodes 14 (connected to octoclock 2) and 10 (connected to octoclock 1)
Between nodes 10 (connected to octoclock 1) and 27 (connected to octoclock 3)
For more (updated) info on the octoclocks: